• 专利附录
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    • 专利摘要:
    System and method of hardware configuration of programmable control, test and measurement instruments. System and method of hardware configuration of a programmable instrument (10) of control, test and measurement comprising an fpga (30) integrated with two sections, a first static section (31) and a dynamic section (33), connected by a logical interface (32). The static section (31) comprises implemented code and predetermined factory (34), previously optimized, while the dynamic section (33) comprises programmable code (35) by the user. This greatly simplifies the configuration of the programmable instrument (10) by the user, in addition to reducing the compilation times and optimizing the operation and performance of the fpga (30). (Machine-translation by Google Translate, not legally binding)
    公开号:ES2562153A1
    申请号:ES201531184
    申请日:2015-08-10
    公开日:2016-03-02
    发明作者:Néstor Hugo OLIVERIO；Marc ALMENDROS PARRA
    申请人:Signadyne Spain SL；
    IPC主号:
    专利说明:

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    System and hardware configuration method of programmable control, test and measurement instruments.
    object of the invention
    The present invention belongs to the technical field of electronics and, in particular, applies to the industrial area of the programmable instruments to execute control, test and / or measurement functions.
    background of the invention
    During the last years, the requirements imposed on the programmable control, test and / or measurement instruments have been significantly increased. The requirements have increased significantly in terms of number of inputs and outputs, acquisition speed and processing capacity. Additionally, the need to process a large amount of data in real time, joins the need to adapt this processing to various particular applications with the same hardware platform and often in a very short time.
    FPGA technology ('field programmable gate array arrangements') provides a very promising alternative to meet these challenges, given its reconfigurable character and high processing capacity. However, to implement the necessary configurations for the correct operation of the control, test and measurement instruments, advanced knowledge of logical hardware is necessary, as well as highly specialized design tools for FPGA, having to define interconnections Physics and propagation times of internal signals. This means that to implement FPGA-based systems, experts in the field are required and also the implementation and start-up times of these systems are very long, even for expert users. Control, test and measurement systems require the features offered by FPGAs but they need to be quick and simple to use and start up without the user having to be an expert in hardware programming.
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    Some commercial solutions provide hardware that allows control, test and measurement applications that include an FPGA and provide the user with a framework project -framework, in English- for the software tool provided by the FPGA manufacturer included on the instrument This framework project includes the necessary components to interact with the fixed hardware of the equipment and the user can modify it to add the functionalities he wishes. The problem with these systems is that it requires users who are experts in FPGA, which is usually not the case for control, test and measurement engineers, and also the development and commissioning times are very long, which also greatly limits their application to control, test and measurement.
    In order to simplify the process, there are some graphic tools that allow to implement FPGA code more easily, but since they are not designed for any specific instrument, they still require complex interactions for their implementation on the hardware of each particular instrument, being typically It is necessary to use the software tools provided by the FPGA manufacturer included in the instrument and use some framework project as in the previous case. That is, these graphic tools do not natively contemplate the implementation on commercial instruments, which is a very complex task and suffers from similar problems to those described for the previous solution.
    Other solutions provide modular instruments that include an FPGA and specific software to program these instruments, which consists of a graphical programming environment that adapts a software programming language based on loops, conditional, etc., to FPGA hardware programming. The high-level graphic tool simplifies the process of programming the FPGA hardware for the user, but at the cost of a reduction in performance due to a lower possibility of optimization compared to a programming carried out with advanced tools. In addition, the software programming mechanism adapted to hardware has serious drawbacks that, depending on the use made by the user, often result in very poor use of the FPGA.
    In all the aforementioned cases, during the FPGA hardware customization process of the instrument by the user, the entire FPGA logic is fully implemented, and this occurs every time the user changes some functionality at least. This added to the limited optimization capacity of a user not
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    expert, seriously compromises the performance and operation of both the functions induced in the manufacturer's libraries and the additional functions developed by the user. Also for this reason, the compilation and start-up times of the instrument can be prohibitively long.
    Ultimately, there is still a need in the state of the art for a hardware configuration method and system for programmable control, test and measurement instruments that allow dynamic configuration of said instruments in a simple and optimized way, without the need for specific knowledge. FPGA and reducing the waiting times associated with changes in said configuration.
    description of the invention
    The present invention serves to solve the problem mentioned above, solving the problems presented by the solutions mentioned in the state of the art, by means of a partial reconfiguration of the FPGA that separates: a dynamic programmable FPGA logic by the user and a predetermined static FPGA logic Factory implemented. Both logics are reconfigurable, but static logic is developed at the factory by experts, while dynamics is implemented with simplified tools for the end user, who does not need knowledge of FPGA programming.
    In the context of the invention, the following concepts are defined and used:
    - User code: It is the "high level" source code that implements the user FPGA functionalities to customize the operation of the instrument. programmable control, test and / or measurement
    - FPGA Logic: It is the result of the process of implementing the FPGA code in the FPGA and includes the logic gates and all the internal components that make up the FPGA, its positioning and interconnection within the FPGA.
    ■ Dynamic FPGA Logic: It is the result of the implementation of the user code.
    ■ Static FPGA Logic: It is preset FPGA logic, developed and implemented at the factory which cannot be modified by the user.
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    - Static / dynamic section: it is an area of the FPGA destined to contain the static / dynamic FPGA logic.
    In a first aspect of the invention a hardware configuration system of a programmable control, test and measurement instrument is presented, comprising an FPGA integrated in said instrument, giving it dynamic programming or reconfiguration capabilities. The FPGA comprises two sections:
    - A static section that includes at least one default static FPGA logic implemented at the factory. Said static FPGA logic can comprise essential functionalities of the instrument whose complexity exceeds the knowledge of an average user, as well as additional functionalities whose low-level optimization with advanced tools is a chore for its correct operation in the FPGA.
    - A dynamic section that includes at least one programmable dynamic FPGA logic by the user. Since the user uses the functionalities provided by the FPGA logic of the static section and does not modify the static section, the implementation of the dynamic FPGA logic with the new user functionalities is greatly simplified. In addition to not modifying the static FPGA logic at all in the dynamic FPGA logic implementation process, the optimized operation of the factory functionalities is maintained regardless of the customizations introduced by the user. Also, the reprogramming of the dynamic section does not affect the static section of the FPGA, so the static FPGA logic can continue its operation during the reprogramming or reconfiguration of the dynamic FPGA logic.
    The default static FPGA logic determines a fixed logical interface that allows interconnecting any dynamic FPGA logic with the static FPGA logic, which allows the user to make use of the factory functionalities and interconnect them with the dynamic FPGA logic developed by it. Customize the instrument.
    Preferably, the static section can be configured with multiple factory-set static FPGA logics implemented by the user. Also preferably, the dynamic section can be configured with multiple interchangeable dynamic FPGA logics during the operation of the static FPGA logic and the rest of the
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    instrument. Likewise, both the static and dynamic sections can be subdivided into static and dynamic subsections respectively, so that any of the subsections can be reconfigured while the others continue to function. The FPGA logics can be stored in the user's computer or in a volatile or non-volatile memory of the same instrument. The exchange between different FPGA logics can be carried out by user indication, or even in an automated way when conditions described by the programmable code itself are met. In addition, FPGA logics can be programmed in non-volatile memory of the module for the configuration of the module automatically at startup.
    Preferably, the system comprises a user interface for programming the dynamic section, that is, for the development of the user code containing the instructions or functions to customize the control, test and measurement instrument. Through the user interface, the user enters high-level instructions or functions that are preferably converted to FPGA logic for dynamic sectioning in an implementation server. According to preferred options, the server can be integrated into the same software together with the user interface, or be integrated into separate software that can run locally or remotely, thus providing cloud deployment services.
    Preferably, the system comprises one or more static hardware profiles for each instrument. Static hardware profiles consist of a static profile for the user interface and the corresponding static FPGA logic and logical interface. Preferably, the static profile of the user interface consists of a simplified description of the associated static FPGA logic, consisting of blocks that describe the functionalities of the static FPGA logic and include the ports of the logical interface between the static and dynamic FPGA logic. The user interface allows selecting among the static profiles available for each instrument on which the user performs the programming of the new functionalities. The different hardware profiles include functionalities in the static section implemented in the factory oriented to specific control, test and measurement applications of the instrument and that, due to their complexity, require an implementation and optimization carried out by experts with advanced tools.
    Preferably, the user interface also includes standard buses, buses specifically adapted to the characteristics of the hardware and data generated by
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    each instrument Buses are groups of signals and data that allow to communicate complex actions or data between functions without the need to know or expressly and individually manipulate the data and signals that make up the bus. Likewise, the system preferably comprises at least one libreha with predefined models that the user can use for programming the dynamic section. These librehas, as well as the static profiles, natively include master and slave interfaces for the specific buses, processing and manipulating the signals and complex data of the instrument transparently to the user, so that it can program new functionalities in a simple way. , without having to implement complex processing techniques and different signal management according to each instrument.
    Preferably, the user interface provides additional functionalities to the user, such as code validation and / or latency calculation, information that is preferably provided to the user during code development. According to preferred implementation options, the user interface can be a graphic interface, a text interface, or an interface that combines both modalities.
    In a second aspect of the invention a hardware configuration method of a programmable control, test and measurement instrument is presented, said instrument comprising an integrated FPGA with a dynamic section and a static section connected through a logical interface. The method comprises the following steps:
    - Execute a dynamic FPGA logic developed by a user in the dynamic section. The configuration of the dynamic section according to this logic is independent of the configuration of the static section of the FPGA, so it can be done while the static FPGA logic remains operational. In addition, the dynamic section can in turn be divided into subsections so that one subsection can be reconfigured while the others remain operational. Preferably, dynamic FPGA logic is generated in an implementation server from the high-level user code developed by the user through a user interface. The server can be run locally or remotely according to preferred method options. Likewise, the interface can be graphic, textual, or combine both options, as well as incorporating predefined component books for the dynamic section.
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    - Preferably, the method may comprise selecting from a plurality of preset static FPGA logics implemented at the factory to reconfigure the static section. Note that switching between static FPGA logics, called instrument hardware profiles, implies reconfiguration of the static section, but being previously implemented in factory FPGA logic, the time in which the instrument remains inoperative is minimized, while its versatility is increased without compromising its operation or performance. The static section can be divided into subsections so that a static subsection can be reconfigured while the others remain operational.
    - Also preferably, the method may comprise the configuration in the dynamic section of multiple dynamic FPGA logics developed by the user, said logics being interchangeable by explicit user instruction or by the instrument's own automated behavior. These logics can be stored in the user's computer, in a volatile memory of the instrument or in a non-volatile memory of the same instrument for automatic configuration at startup.
    - Preferably, the method includes the use of standard buses and specific buses to each instrument for the interconnection of the functions used by the user, so that complex interconnections are carried out without knowing the internal details of the signals and data on the bus , that is, as a single signal. The functions of the libraries and interfaces with static FPGA logic include master and slave interfaces for these buses so that they process and manipulate these complex data buses transparently to the user.
    - Preferably, the method comprises checking in real time during the programming of the user code the validity of the connections, allowing only those valid connections and suggesting to the programmer actions to make the connections correctly.
    - Preferably, the method also includes automatically calculating latencies associated with the user code and preferably displaying this information during its development to accelerate the process and simplify a very
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    important in FPGA hardware programming, without the need to perform simulations or implement FPGA logic and run it in hardware, processes that usually require a lot of time, especially implementation.
    - Preferably, the method comprises locally validating the programmable code developed before starting the dynamic FPGA logic implementation phase, which usually requires an important time. That is, the design software itself allows validating the code developed by the user to verify general operating parameters, interconnections between user functions and with static FPGA logic, resources used and other parameters that allow problems to be detected at an early stage before Start the implementation in the FPGA.
    The method and the system of the invention manage to make the generation stage of the user FPGA hardware or dynamic FPGA logic independent of the factory-set static FPGA logic that provides the essential functions -core functions, in English- of the instrument and over which the user develops the application. Thus, the factory default static FPGA logic and dynamic user FPGA logic are implemented and optimized separately, since static factory logic is not modified during user customization of the module. This allows to reduce significantly the times and the difficulty of implementation of the dynamic FPGA logic developed by the user, which as a consequence can be developed with simplified tools usable by users without experience in FPGA programming. While at the same time it is guaranteed that in the process of personalization of the instrument the factory functionalities will not be affected during the implementation of the dynamic FPGA logic. The factory FPGA logic provides the essential functionalities of the module, as well as complex additional functionalities important for certain instrument applications, which are developed and optimized at the factory with complex techniques and advanced low-level tools that allow very efficient use of the FPGA resources and achieve maximum performance, without which many of these very demanding functionalities cannot be implemented. Additionally, the static-dynamic separation allows to keep the static FPGA logic completely protected and hidden from the user, safeguarding the know-how of the developers. Finally, the use of partial reconfiguration of the FPGA for the dynamic or static section allows the user to reprogram part of the FPGA while other parts continue
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    operating in the application, and even that a part of the system by hardware triggers the reconfiguration of itself or another part.
    brief description of the figures
    A series of drawings that help to better understand the invention and that expressly relate to an embodiment of said invention that is presented as a non-limiting example of this is described very briefly below.
    FIGURE 1.-. It shows a block diagram of the architecture of a programmable instrument for control, test and measurement according to a possible embodiment of the invention.
    FIGURE 2.-. It presents a block diagram of a programmable instrument configuration system, as well as the information exchanged between said blocks, according to a possible embodiment of the invention.
    FIGURE 3.-. It exemplifies a possible embodiment of the user interface of the invention.
    preferred embodiment of the invention
    In this text, the term "comprises" and its derivations (such as "understanding", etc.) should not be understood in an exclusive sense, that is, these terms should not be construed as excluding the possibility that what is described and defined can include more elements, stages, etc.
    Given that the process of implementing an FPGA consists in generating the information necessary to determine the interconnections and positioning of the internal logical components of said FPGA, in this text, the term 'FPGA logic' should be understood as a set of information that defines these interconnections and positioning. In particular, and as detailed throughout the description, a 'static FPGA logic' refers to a set of interconnections and internal component positions of the factory-set FPGA preset, while a 'dynamic FPGA logic' refers to to a set of interconnections and positioning of internal components of the FPGA resulting from implementing the user code.
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    Figure 1 exemplifies a programmable instrument (10) for control, test and measurement on which particular implementations of the method and system of the invention are applied. In a preferred implementation, the programmable instrument (10) is a modular instrument of a PXI express platform (PCI extensions for instrumentation, from the 'PCI extensions for Instrumentation') or PCI express (Interconnection of Peripheral Components Express, from the English 'Peripheral Component Interconnect Express'), although there may be implementations on any other platform for control, test and measurement instruments compatible with FPGA technology.
    The programmable instrument (10) comprises a fixed hardware (20) managed by an FPGA (30). The FPGA (30) comprises one or more input and / or output ports (50), as well as a communication bus (40), which may also be accompanied by ports for any other signal required by the FPGA (30), such as clock signals, etc. Note that the hardware configuration method and system of the programmable instrument (10) act only on the FPGA (30), therefore being independent of the other components of the programmable instrument (10).
    The FPGA comprises a static section (31) and a dynamic section (33), connected through a logical interface (32). The static section (31) comprises static FPGA logic (34) implemented and optimized at the factory, while the dynamic section (33) comprises dynamic FPGA logic (35) programmable by the user. The static FPGA logic (34) includes the essential functionalities - core functions, in English - of the instrument and those whose low-level implementation and advanced optimization are practical for the operation of the programmable instrument (10).
    The static FPGA logic (34) implements all the necessary functions to control the fixed hardware (20), such as: PCIe communication (Interconnection of Peripheral Components Express, from the English 'Periferal Component Interconnect Express'), DMA (direct access memory , from English 'Direct Memory Access'), RAM (random access memory, from English 'Random Memory Access) and non-volatile, ADC (analog to digital signal converter, from English' Analogue to Digital converter) and DAC ( Digital to analog signal converter, from English Digital to Analogue converter), etc.
    The static FPGA logic (34) also implements important functions for the specific operation of the instrument. For example in a generation instrument
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    Analog signals, the static FPGA logic (34) can include the functionalities of generating periodic signals, generating arbitrary signals, modulators, filters, etc.
    The static FPGA logic (34) implements the functionalities that usually have very strict performance requirements and that require the use of complex advanced tools for its implementation, such as DDR3 memory interfaces with transfer rates of tens of GigaBytes per second or interfaces PCI Express of several GigaBytes per second. This type of functionality requires the use of very high working frequencies and sizes of data and very complex logic that requires an expert analysis at a low level to achieve its proper functioning.
    Figure 2 presents in greater detail the elements of the system involved in the programming of the dynamic section (33). The user enters the high-level instructions and functions that form the user code (61) through a user interface (60). The user interface (60) comprises a static profile (83) on which the user implements the user code (61). Preferably, the user selects from a library of static profiles (82a) which he wishes to use according to the options of each specific instrument. The static profile library (82a) is part of the hardware profile library (82) which also includes the static FPGA logic library (82b), which includes a static FPGA logic (34) and the corresponding logical interface (32) to each static profile (83). The Hardware profile library (82) includes one or more hardware profiles for each instrument. Each hardware profile is composed of the static profile (83) and its corresponding static FPGA logic (34) which in turn defines a logical interface (32). The static profile (83) consists of a simplified description of the static FPGA logic, which captures its functionalities and incorporates the logical interface (32) for the user to implement the user code (61) and connect it to the functionalities provided by logic Static FPGA (34). Said user code (61) is transmitted to an implementation server (70), which combines it with models (81) of one or more libraries (80) to generate the dynamic logic (35) that is executed in the dynamic section (33). The server uses information from the static FPGA logic (34) and the corresponding logical interface (32) for the implementation of the dynamic FPGA logic (35) compatible with the static FPGA logic (34) according to the selected hardware profile. The models (81) of the libraries (80) make it easy for the user to program the dynamic section (33), but unlike the static FPGA logic, they are customizable. The static FPGA logic (34) selected with the
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    Hardware profile is configured in the static section (31) of the FPGA. The static and dynamic FPGA logic are configured independently in the FPGA, so that multiple dynamic FPGA logics can be programmed for the same static FPGA logic while the static FPGA logic and the rest of the instrument continue to function, enabling the very rapid change of logic Dynamic FPGAs developed by the user.
    The implementation server (70) can be integrated in the same user interface software (60), or be a local server running on the same computer as the user interface, as a remote server, connected to the software of the user interface. user interface (60) via wired or wireless connection means. In particular, the remote server provides cloud deployment services.
    Figure 3 exemplifies the user interface (60) for the development of the user code (61) for programming the dynamic section (33). In this case, it is a graphical interface based on interconnected blocks. On the main screen you can see three types of blocks:
    - Static blocks (62), corresponding to functionalities of the static FPGA logic (34). The static blocks (62) are part of the static profile (83), the user therefore does not modify said static blocks (62), but uses their logical ports to connect them with the rest of the blocks of their design. The logical ports of the static blocks (62) make up the logical interface (32) of the FPGA. Note that the static blocks (62) are not necessarily a reliable representation of the implementation of the factory code, that is, they can be a simplified view that does not reflect the complexity of the actual implementation of the static functionalities represented.
    - Dynamic blocks (63), whose content is predefined, for example from the models (81) of the libreha (80), which the user uses to perform the functions of dynamic logic (35), and therefore can be selected, modified and / or deleted by the user
    - User blocks (64), programmed entirely by the user. The user blocks (64) can be implemented using the user interface (60) or imported from any other FPGA hardware programming tool.
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    To facilitate user programming tasks, the user interface (60) can comprise a dynamic code by default that implements the factory functionalities that characterize the instrument and make it fully functional and that serves the user as a basis for Development of your code. In addition, the user interface (60) can comprise other elements, such as a list of dynamic blocks included by factory default removed (65), or available connection ports (66), as well as any other element that simplifies the use of the software and the development of the user code. The user interface (60) may comprise selection means that allow the user to select from multiple static profiles (83) available for the specific instrument, as well as configure different dynamic (35) and static (34) logic in the instrument. Different static profiles (83) and their corresponding static FPGA logic (34) for the same instrument include different high-performance blocks that are important for a group of applications, which require implementation with very advanced knowledge and include them as libraries for the area dynamically hinder its implementation and compromise the correct operation of the programmable instrument (10).
    The user interface includes standard buses and also specific buses for each instrument, which group signals and complex data in a single connection to simplify and accelerate the development of the code by the user. Standard buses include AXI connections, memory access, etc., while specific buses depend on the data generated and processed by each instrument. Thus, for example, modules for the acquisition or generation of signals of several hundreds of megahertz or gigahertz require the use of data paralysis techniques to be manipulated within the FPGA, these techniques extremely complicate the programming of the instruments. By using specific buses the user can manipulate the data without knowing this complexity since both the factory and library blocks include specific interfaces for these buses and manipulate this complex data natively and transparently for the user as a single signal. .
    The user interface (60) may comprise additional functionalities such as code validation or latency calculation. With the latency information of each block, the software allows you to quickly visualize during the editing the delays in the different connections of the diagram, as well as adjust these delays very easily in diagrams with multiple blocks.
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    The user interface (60) can comprise simulation functions of the user code that incorporate models of the static and dynamic blocks and that allow to perform behavioral simulations and visualize the signals at the different points of the diagram. In addition, the user interface (60) can allow generating a virtual instrument that the system recognizes as a real instrument, so that the user software can interact with the virtual instrument as if it were a real one with the user FPGA logic already implemented and configured in the instrument. In this way, the operation of the instrument can be simulated within the control, test and measurement application, generating the real stimuli that the real instrument will receive but with greater control and possibility to visualize all the simulation information of any point of the diagram without the need for Implementing user logic and additional depuration logic in the real instrument, which usually requires the time required for the implementation of FPGA logic and also the hardware debugging capabilities usually have more limitations than simulations.
    The user interface (60) can comprise debugging functionalities that allows adding points for debugging or debugging (hardware), for which the software automatically generates the necessary hardware logic. Once these debug points have been generated, the software receives from the instrument (10) debug information through some of the communication buses available in the instrument (for example PCI Express), and displays it through the user interface ( 60). The static section (31) may comprise specific static profiles with specific functionalities to perform said purification.
    Once the user has finished his design through the user interface (60), the software generates the dynamic FPGA logic (35) corresponding only to the dynamic section (33) and the logical interface (32) that defines the interconnections between the dynamic section (33) and the static FPGA logic (34). The software first processes and validates the user code (61) locally and then sends it to the implementation server (70) for the generation of the dynamic logic (35) and the corresponding partial reconfiguration file of the dynamic section (33 ). Before proceeding to the implementation on the implementation server (70), the software locally validates the correct realization of the user code, its interconnection with the static FPGA logic and verifies that the resources used are available in the dynamic section (33). The implementation server (70) joins the user code already processed locally with the possible corresponding connection files
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    to the blocks of the libraries (80), generating a partial configuration file for the dynamic section (33) compatible with the static FPGA logic (34), which reflects the positioning and interconnection of the dynamic FPGA logic (35). In the implementation process only dynamic FPGA logic (35) is generated, so the time and difficulty of implementation are much less than regenerating the complete FPGA logic (30) and also the static FPGA logic is not modified at all. (34) of the static section (31) so that the performance and optimizations of all factory functionalities are maintained. With the partial configuration file, the user can reprogram the dynamic section (33) of the FPGA (30) at any time while the static logic and the rest of the module continue to function.
    The load management of the new partial configuration of the FPGA (30), that is, the configuration of the dynamic logic (35) of the user in the dynamic section (33) can be carried out from the user interface itself (60) or, through the libraries provided, from any other software application. In this way, different previously generated dynamic configurations can be available and dynamically loaded as the control, test and measurement application software requires different hardware processing. The partial reconfiguration information can be programmed in the FPGA (30) directly, in a volatile memory of the instrument or in a non-volatile memory included in the instrument for automatic loading at startup. In addition, more than one reconfiguration can be stored in volatile or non-volatile memory, allowing to dynamically modify the selection or configuration of the hardware (20) of the programmable instrument (10).
    The loading of the different static FPGA logics corresponding to the different static profiles (83) can be carried out in a similar way to the configuration of the dynamic FPGA logic, from the user interface (60) or by means of supplied libraries. In addition, both the dynamic section (33) and the static section (31) can be divided into subsections so that the subsections can be reprogrammed while the others continue to function.
    In view of this description and figures, the person skilled in the art may understand that the invention has been described according to some preferred embodiments thereof, but that multiple variations can be introduced in said preferred embodiments, without departing from the object of the invention such and as claimed.
    权利要求:
    Claims (34)
    [1]
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    1. A hardware configuration system of a programmable control, test and measurement instrument (10) comprising an integrated FPGA (30), characterized in that the FPGA (30) comprises:
    -a static section (31) comprising at least one preset static FPGA logic (34);
    - a dynamic section (33) comprising at least one dynamic FPGA logic (35) programmable by a user;
    -a logical interface (32) that connects the static section (31) and the dynamic section (33).
    [2]
    2. The configuration system, according to revindication 1, characterized in that the static section (31) comprises a plurality of static FPGA logics (34) preset selectable by the user and reconfigurable during the operation of the programmable instrument (10).
    [3]
    3. The configuration system, according to any of the preceding claims, characterized in that the dynamic section (33) comprises a plurality of dynamic logics (35) programmable by the user and reconfigurable during the operation of the programmable instrument (10) and while the static section (31) continues to work.
    [4]
    4. The configuration system, according to any of the preceding claims, characterized in that the static section (31) and the dynamic section (33) comprise a plurality of subsections and at least one of the subsections is individually reconfigurable by selection of the user while the remaining subsections continue to work.
    [5]
    5. The configuration system, according to any of the preceding claims, characterized in that it comprises at least one hardware profile for each instrument (10), the hardware profile comprising the static FPGA logic (34) and the logical interface ( 32) implemented and optimized at the factory to adapt the instrument (10) to specific requirements of different control, test and measurement applications.
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    [6]
    The configuration system, according to any of the preceding claims, characterized in that it comprises storing one or more static FPGA logics (34) and dynamic FPGA logics (35) in an instrument memory (10), which is selected from volatile and non-volatile memory.
    [7]
    7. The configuration system according to claim 6, characterized in that in the case of non-volatile memory, the stored static FPGA logics (34) and FPGA logics (35) are used to automatically reconfigure the instrument (10) in startup.
    [8]
    The configuration system, according to any of the preceding claims, characterized in that it comprises a user interface (60) through which the user enters high level instructions and functions that form a user code (61) to program the dynamic section (33) and connect it with functions of the static FPGA logic (34) through the logic interface (32).
    [9]
    9. The configuration system, according to claim 8, characterized in that the user interface (60) comprises at least one static profile (83) for each instrument (10), each static profile (83) associated with the logic Static FPGA (34) and the logical interface (32), and where the static profile (83) describes the functionalities of the associated static FPGA logic (34), in the form of static models (62) that include ports of the logical interface (32) that the user uses to interact in the user code (61) with the static FPGA logic (34).
    [10]
    10. The configuration system according to any of claims 8-9, characterized in that the user interface (60) locally validates the user code (61) before being sent to the implementation server (70) to be implemented in dynamic FPGA logic (35) for the dynamic section (33).
    [11]
    11. The configuration system according to any of claims 8-10, characterized in that the user interface (60) calculates latencies associated with the models used in the user code (61) and displays this information during the development and before being implemented in a dynamic FPGA logic (35) for the dynamic section (33).
    5
    10
    fifteen
    twenty
    25
    30
    35
    [12]
    12. The configuration system according to any of claims 8-11, characterized in that the user interface (60) comprises specific functions for debugging the user code (61) and reads debugging information through ports of communication of the instrument (10) and displays the information in real time in the same user interface (60).
    [13]
    13. The configuration system according to any of claims 8-12, characterized in that the user interface (60) comprises simulation functionalities to implement a virtual instrument that the system recognizes as real.
    [14]
    14. The configuration system according to any of claims 8-13, characterized in that the user interface (60) is a graphic interface.
    [15]
    15. The configuration system according to any of claims 8-13, characterized in that the user interface (60) is a text interface.
    [16]
    16. The configuration system according to any of the claims
    above, characterized in that it comprises specific data buses adapted to the particular characteristics of each programmable instrument (10) and that group the complex data and signals generated by the instrument and represent them as a single signal.
    [17]
    17. The configuration system according to any of the claims
    above, characterized in that it comprises at least one library (80) with a plurality of models (81) usable by the user to develop the user code (61) and that include interface ports for the specific data buses to each instrument that manipulate and process the multiple data and signals of the specific buses as a single signal.
    [18]
    18. The configuration system, according to any of the claims
    Previous features characterized in that it comprises an implementation server (70) that converts the high level instructions and functions that form the user code (61) into dynamic FPGA logic (35) compatible with static FPGA logic (34) and the logical interface (32), and the implementation server (70) generates partial configuration information to program the dynamic section (33).
    5
    10
    fifteen
    twenty
    25
    30
    35
    [19]
    19. The configuration system, according to claim 18, characterized in that the implementation server (70) is integrated in an edition software comprising the user interface (60).
    [20]
    20. The configuration system according to claim 18, characterized in that the implementation server (70) is integrated in a remote software.
    [21]
    21. The configuration system according to claim 20, characterized in that the remote software provides cloud implementation services.
    [22]
    22. Method of configuring a programmable instrument (10) for control, test and measurement comprising an integrated FPGA (30), characterized in that it comprises executing a dynamic FPGA logic (35) programmed by a user in a dynamic section (33) of the FPGA (30), said dynamic section (33) being connected through a logical interface (32) to a static section (31) comprising at least one static FPGA logic (34) implemented and preset.
    [23]
    23. The method of configuration, according to claim 22, characterized in that it comprises receiving a selection from the user among a plurality of hardware profiles comprising static FPGA logic implemented and preset configurable in the static section (31) and interchangeable during operation of the instrument (10) programmable to adapt it to different requirements of specific control, test and measurement applications.
    [24]
    24. The configuration method according to any of claims 22-23, characterized in that it comprises configuring in the dynamic section (32) a plurality of dynamic FPGA logics (35) interchangeable during the operation of the programmable instrument (10) and while the static FPGA logic (34) continues to function.
    [25]
    25. The method of configuration according to any of claims 22-24, characterized in that it comprises receiving high-level instructions and functions that form a user code (61) to program the dynamic section (33) through a user interface (60).
    [26]
    26. The configuration method according to claim 25, characterized in that it comprises converting the high level instructions and functions of the user code (61) into
    5
    10
    fifteen
    twenty
    25
    30
    Dynamic FPGA logic (35) for the dynamic section (33) compatible with static FPGA logic (34) on an implementation server (70).
    [27]
    27. The configuration method according to claim 26, characterized in that the step of converting the high level instructions and functions of the user code (61) into dynamic FPGA logic (35) is executed on a server (70) integrated in an edition software that includes the user interface (60).
    [28]
    28. The configuration method according to claim 26, characterized in that the step of converting the high level instructions and functions of the user code (61) into dynamic FPGA logic (35) is executed on a server (70) remote.
    [29]
    29. The configuration method according to any of claims 22-28, characterized in that it comprises locally validating the user code (61) before being implemented in dynamic FPGA logic (35) for the dynamic section (33).
    [30]
    30. The configuration method, according to any of claims 22-29, characterized in that it comprises calculating latencies associated with the user code (61) before being implemented in the dynamic FPGA logic (35) for the dynamic section ( 33).
    [31]
    31. The method of configuration, according to any of claims 22-30, characterized in that it comprises receiving high-level instructions and functions (61) through a graphical interface.
    [32]
    32. The configuration method, according to any of claims 22-31, characterized in that it comprises receiving the high level instructions and functions of the user code (61) through a text interface.
    [33]
    33. The method of configuration according to any of claims 22-32, characterized in that it comprises using specific data buses for each instrument so that the complex data and signals contained in the bus are manipulated and interconnected between functions such as Only signal.
    [34]
    34. The configuration method according to any of claims 22-33, characterized in that it comprises generating the dynamic FGPA logic (35) using at least one library (80) with a plurality of models (81), which include interfaces for some buses of each instrument (10) and that process the signals and data of the buses as a single signal.
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    同族专利:
    公开号 | 公开日
    US20170123394A1|2017-05-04|
    ES2562153B2|2016-10-07|
    US10324436B2|2019-06-18|
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    ES201531184A|ES2562153B2|2015-08-10|2015-08-10|System and hardware configuration method of programmable control, test and measurement instruments|ES201531184A| ES2562153B2|2015-08-10|2015-08-10|System and hardware configuration method of programmable control, test and measurement instruments|
    US15/232,775| US10324436B2|2015-08-10|2016-08-09|System and method for programmable control instruments, test and measurement hardware configuration|
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